IP-blocks

 

MALT design center develops digital and analog IPs according to customer requirements. The company’s portfolio includes both Soft IPs and Hard IPs for design of modern VLSI and SoC. IPs are developed for specific technological process of a particular factory according to the requirement specification. Occasionally, we have to develop interface blocks for VLSI integration, when using third-party manufacturers’ IPs.

 

IP PORTFOLIO INCLUDES:

 

  • IPs for modern crypto accelerators on such standards as DES, AES, SHA, etc.

 

  • IPs for voltage references and thermal sensors (LDO, t).

 

  • IPs for phase-locked loops and controllable delay lines (PLL, DLL).

 

  • IPs for high-speed transmission channels (LVDS, SSTL).

 

  • IPs for data serialization and clock recovery (PMA).

 

  • IPs for scrambling and data encryption (PCS 8/10, 64/66).

 

  • IPs for high-speed serial interfaces (SERDES).

 

  • IPs for Ethernet logical layer 10/100/1G/10G (Ethernet MAC).

 

  • IPs for Ethernet physical layer 10/100/1G/10G (Ethernet PHY).

 

  • IPs for DDR 1/2/3/4 logical layer (DDR logic).

 

  • IPs for memory controllers RLDRAM (logic).

 

  • IPs for high-speed static memory controllers (QDR SRAM logic).

 

  • IPs for periphery (I2C, I2S, SPI, UART, etc.).

 

We implement after-sale support in terms of optimization, interfaces, compatibility and IP integration in SoC. We provide software updates for our IPs. We guarantee information security and legal transparency for the supplied IPs.

 

 

PLEASE FEEL FREE TO CONTACT US TO GET MORE INFORMATION ABOUT MALT FEATURES!