2011
Project start

20.09.2011 The team has been formed for 1000-core processor development

 

 

2012
10-core prototype on Virtex5 has been built

06.05.2012 A general-purpose RISC core has been selected and tested for the prototype of 10-core system on FPGA

17.09.2012 10-core Xilinx Virtex5 processor with tagged shared memory controller on FPGA has been built

22.09.2012 The Minix3 core and basic services have been ported to the 10-core processor

2013
49-core prototype on Virtex6 has been built

18.03.2013 PHP support is demonstrated on the prototype of our processor. This is the first PHP script in the world written without using x86 Minix!

08.04.2013 Original on-chip bus for merging hundreds of processing cores is developed

05.10.2013 49-core processor on Xilinx Virtex6 FPGA with lightweight-thread support has been built

28.11.2013 The developed architecture is named ‘MALT’!

2014
210-core prototype on Virtex7 is built

21.04.2014 MALT architecture porting to FPGA Xilinx Virtex7 is started

10.10.2014 A new smart memory controller is developed (DMA and atomic operations)

28.12.2014 210-core processor on FPGA Xilinx Virtex7 is built

2015
Coprocessor Leopard has been designed ‘from a scratch’

25.03.2015 The first MALT prototype on FPGA with specialized accelerators has been developed

16.08.2015 The development of MALT-processors with vector and mixed architecture has been started

22.11.2015 The processor element Leopard for vector MALT coprocessor has been designed

 

 

 

2016
ASM, C-compiler for Leopard, has been developed

Virtex

25.02.2016 Assembler and emulator for programmed accelerator have been developed as parts of MALT

24.03.2016 96-core MALT prototype with mixed architecture on FPGA Xilinx Virtex7 has been built

16.05.2016 We've started to create the MALT-Cv1 netlist using 28 nanometer TSMC technology

20.07.2016 C-compiler for programmed accelerator for the MALT-Cv1 has been developed

15.10.2016 The debugging set (emulator, debugger, profiler) for the MALT-Cv1 has been released

 

 

 

2017
96-core MALT has been manufactured ‘in silicon’

96core

 

 

 

18.01.2017 The design of the MALT-Cv1 96-core processor’s front end has been completed, it is going to be manufactured at TSMC 28nm factory

06.05.2017 The design of the MALT-Cv2 processor (performance-per-watt is 5 times higher compared to the MALT-Cv1) has been started

07.07.2017 The first-generation 96-core processor project has been sent to MPW manufacturer

25.12.2017 The first samples of MALT-Cv1 have been received from TSMC foundry

 

 

 

2018
The synthesis of MALT-Cv2

OpenCL

 

02.02.2018 Software development kit 1.1 has been released

05.03.2018 Software development kit 1.2 has been released

03.04.2018 Software development kit 1.3 has been released

19.04.2018 ‘ExpoElectronica 2018’ exhibition has been ended

12.09.2018 Software development kit 1.5 released

30.11.2018 MALT has been presented in Electronica-2018 in Munich

07.12.2018 The development of the behavior model and the synthesis of the MALT-Cv2 processor have been completed

 

 

 

2019
The MALT-Cv2 released

OpenCL

 

 

 

01.03.2019 Software development kit 1.6 has been released

18.04.2019 MALT project has been presented at ExpoElectronica-2019

28.05.2019 Debugging board for MALT processor

05.07.2019 Software development kit 1.7 has been released

14.07.2019 Closed testing of a virtual laboratory is being conducted for operations with MALT processors

01.09.2019 500-core processor project MALT-Cv2 has been sent to TSMC

06.09.2019 Software development kit 1.8 has been released

02.10.2019 International Forum Microelectronics 2019 was held

 

 

 

2020
The 16 nm process launching

OpenCL

 

 

 

19.02.2020 16 nm PDK from TSMC has received

18.03.2020 The first samples of MALT-Cv2 have been received

29.06.2020 New development board with MALT-Cv2

4Q2020 Demonstration of the first prototype on a network processor FPGA for SDN

4Q2020 Update of the WEB SDK for MALT, new examples and platforms