20.09.2011 The team has been formed for 1000-core processor development.

06.05.2012 A general-purpose RISC core has been selected and tested for the prototype of 10-core system on FPGA.

17.09.2012 10-core Xilinx Virtex5 processor with tagged shared memory controller on FPGA has been built.

22.09.2012 An emulator with x86 lightweight thread architecture has been developed. The Minix3 core and basic services have been ported to the architecture.

18.03.2013 PHP support is demonstrated on the prototype of our processor. This is the first PHP script in the world written without using x86 Minix!

08.04.2013 Original on-chip bus for merging hundreds of processing cores is developed.

05.10.2013 49-core processor on Xilinx Virtex6 FPGA with lightweight-thread support is built.

28.11.2013 The developed architecture is named ‘MALT’.

21.04.2014 MALT architecture porting to FPGA Xilinx Virtex7 is started.

10.10.2014 A new smart memory controller is developed (DMA and atomic operations).

28.12.2014 210-core processor on FPGA Xilinx Virtex7 is built.

25.03.2015 The first MALT prototype on FPGA with specialized accelerators has been developed.

16.08.2015 The development of MALT-processors with vector and mixed architecture has been started.

22.11.2015 The processor element Leopard for vector MALT coprocessor has been designed.

10.02.2016 The team has grown significantly!

25.02.2016 An assembler and an emulator for programmed accelerator have been developed as parts of MALT.

24.03.2016 96-core MALT prototype with mixed architecture on FPGA Xilinx Virtex7 has been built.

16.05.2016 We've started to create the MALT-Cv1 netlist using 28 nanometer TSMC technology.

20.07.2016 C-compiler for programmed accelerator for the MALT-Cv1 has been developed.

15.10.2016 The debugging set (emulator, debugger, profiler) for the MALT-Cv1 has been released.

18.01.2017 The design of the MALT-Cv1 96-core processor’s front end has been completed, it is going to be manufactured at TSMC 28nm factory.

06.05.2017 The design of the MALT-Cv2 processor (performance-per-watt is 5 times higher compared to the MALT-Cv1) has been started.

07.07.2017 The first-generation 96-core processor project has been sent to MPW manufacturer.

25.12.2017 The first-generation 96-core MALT processor has been manufactured and successfully tested.

02.02.2018 Software development kit 1.1 has been released.

05.03.2018 Software development kit 1.2 has been released.

03.04.2018 Software development kit 1.3 has been released.

19.04.2018 Participation in the exhibition ‘ExpoElectronica 2018’ in Moscow.

12.09.2018 STL support in C++ for MALT (the developer version).

30.11.2018 MALT has been presented in Electronica-2018 in Munich.

07.12.2018 The synthesis of MALT-Cv2 using 28 nanometer TSMC technology.

01.03.2019 Software development kit 1.6 has been released.

18.04.2019 Presentation of MALT processors at “ExpoElectronica 2019”.

28.05.2019 Debugging board on FPGA for MALT-Cv2 has been released.

05.07.2019 Software development kit 1.7 has been released.

14.07.2019 Closed testing of a virtual laboratory is being conducted for operations with MALT processors.

01.09.2019 MALT-Cv2 project has been sent to TSMC.

06.09.2019 Software development kit 1.8 has been released.

02.10.2019 Opening of virtual laboratory for operations with MALT processors.

4Q2019 Release of MALT SDK for wide range of developers.

4Q2019 Receive of MALT-Cv2 from TSMC and testing them.

4Q2019 Release of debugging kits on MALT-C v2.

1Q2020 Start of project to develope the 16 nm frequency generator.

2Q2020 Demonstration of the first prototype on a network processor FPGA for SDN.

3Q2020 Update of the web SDK for MALT, new examples and platforms.

4Q2020 Sending the 16nm frequency generator project to the factory.