We’ve been thinking long and hard over what name to give our architecture. Eventually, after long deliberation, we’ve decided to name it ‘MALT’ - Manycore Architecture with Lightweight Threads.
This is a significant milestone in the history of the project development. A multi-threaded processor, containing 49 RISC cores, has been implemented on Xilinx Virtex6 FPGA. The architecture, completely redesigned since 10-core prototype, provides the ability to effectively load dozens and hundreds of simple computing cores without conflicts and excessive overhead expenses.
Supercomputer summer classes are held at the Faculty of Computational Mathematics and Cybernetics of the Academy, SRCC, REC "Supercomputer technology" from June 24 to July 6, 2013.
ISC’13 was held June 16-20 in Leipzig, Germany. ISC is the world’s oldest and the most significant high-performance computing conference and exhibition in Europe for the global HPC community.
The development of simple packet bus (SPBUS), enabling to ensure connectivity of hundreds of different devices inside a chip, is finished. SPBUS implementation is written entirely on VHDL without using closed source licensed IP. The developed bus is exceptionally compact in terms of FPGA or VLSI hardware resources usage, along with that it provides delays less than 50 cycles during data transfer.
PHP support has been added to the developed platform. For now, OS Minix3 OS is officially supported on x86-compatible processors only. Different versions of this OS could be found but they're rather experimental. For that reason, without false modesty, we claim, that this is the first PHP script on Minix written without using x86 platform.
We have ported OS Minix3 and its basic services to our processor system. With transition to Minix, we’ve got both multitasking and an opportunity to work with the file system and network interfaces. Moreover, now we have a complete standard C library (earlier we had an abridged version).
Finally! We’ve built and tested our first 10-core processor on FPGA.
For prototyping multicore processors on FPGA we’ve been looking for a core, satisfying such requirements as open flexible architecture, GCC compatibility, minimum size on FPGA, 32-bit RISC architecture, perfect 'layout' on Xilinx FPGAs, performance at least 1 DMIPS/MHz.
Hello world!