News

A new smart memory controller with DMA support has been developed

Details: Published: Friday, 10 October 2014 21:08

A new version of the smart memory controller has been developed and tested. Now the controller maintains block data transfers - usually this calls ‘DMA’ - a system, enabling to copy data from one memory area to another without involving processing cores. The usage of the mechanism allows to increase performance of intensive data exchange tasks in several times. There is a basic set of "real" atomic operations in the controller, for instance, atomic increment is supported.

ISC'14

Details: Published: Thursday, 17 July 2014 11:20

ISC’14 was held June 22-26 in Leipzig, Germany. ISC is the world’s oldest and the most significant high-performance computing conference and exhibition in Europe for the global HPC community.

MALT architecture porting to FPGA Xilinx Virtex7 has been started

Details: Published: Monday, 21 April 2014 14:11

Some time ago we finished the development of 49-core processor prototype on FPGA and now we intend to move forward. Our plans for the nearest future are to increase the number of cores up to 200 and to release a new modification of a memory controller with DMA and atomic increment support.

The developed architecture is named ‘MALT’

Details: Published: Thursday, 28 November 2013 14:21

We’ve been thinking long and hard over what name to give our architecture. Eventually, after long deliberation, we’ve decided to name it ‘MALT’ - Manycore Architecture with Lightweight Threads.

49-core processor on Xilinx Virtex6 FPGA with lightweight-thread support has been built

Details: Published: Saturday, 05 October 2013 17:37

This is a significant milestone in the history of the project development. A multi-threaded processor, containing 49 RISC cores, has been implemented on Xilinx Virtex6 FPGA. The architecture, completely redesigned since 10-core prototype, provides the ability to effectively load dozens and hundreds of simple computing cores without conflicts and excessive overhead expenses.

Supercomputer summer classes

Details: Published: Tuesday, 25 June 2013 09:20

Supercomputer summer classes are held at the Faculty of Computational Mathematics and Cybernetics of the Academy, SRCC, REC "Supercomputer technology" from June 24 to July 6, 2013.

ISC 2013

Details: Published: Tuesday, 25 June 2013 09:14

ISC’13 was held June 16-20 in Leipzig, Germany. ISC is the world’s oldest and the most significant high-performance computing conference and exhibition in Europe for the global HPC community.

Original on-chip bus for combining hundreds of processing cores has been developed

Details: Published: Monday, 08 April 2013 10:17

The development of simple packet bus (SPBUS), enabling to ensure connectivity of hundreds of different devices inside a chip, is finished. SPBUS implementation is written entirely on VHDL without using closed source licensed IP. The developed bus is exceptionally compact in terms of FPGA or VLSI hardware resources usage, along with that it provides delays less than 50 cycles during data transfer.

The first PHP script on Minix written without using x86 platform!

Details: Published: Monday, 18 March 2013 11:00

PHP support has been added to the developed platform. For now, OS Minix3 OS is officially supported on x86-compatible processors only. Different versions of this OS could be found but they're rather experimental. For that reason, without false modesty, we claim, that this is the first PHP script on Minix written without using x86 platform.

The Minix3 core and basic services have been ported to the 10-core processor

Details: Published: Saturday, 22 September 2012 16:54

We have ported OS Minix3 and its basic services to our processor system. With transition to Minix, we’ve got both multitasking and an opportunity to work with the file system and network interfaces. Moreover, now we have a complete standard C library (earlier we had an abridged version).

10-core Xilinx Virtex5 processor with tagged shared-memory controller on FPGA has been built

Details: Published: Monday, 17 September 2012 23:05

Finally! We’ve built and tested our first 10-core processor on FPGA.

General-purpose RISC core has been chosen

Details: Published: Monday, 07 May 2012 03:20

For prototyping multicore processors on FPGA we’ve been looking for a core, satisfying such requirements as open flexible architecture, GCC compatibility, minimum size on FPGA, 32-bit RISC architecture, perfect 'layout' on Xilinx FPGAs, performance at least 1 DMIPS/MHz.