ISC 2013
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- Published: Tuesday, 25 June 2013 09:14
ISC’13 was held June 16-20 in Leipzig, Germany. ISC is the world’s oldest and the most significant high-performance computing conference and exhibition in Europe for the global HPC community.
Original on-chip bus for combining hundreds of processing cores has been developed
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- Published: Monday, 08 April 2013 10:17
The development of simple packet bus (SPBUS), enabling to ensure connectivity of hundreds of different devices inside a chip, is finished. SPBUS implementation is written entirely on VHDL without using closed source licensed IP. The developed bus is exceptionally compact in terms of FPGA or VLSI hardware resources usage, along with that it provides delays less than 50 cycles during data transfer.
The first PHP script on Minix written without using x86 platform!
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- Published: Monday, 18 March 2013 11:00
PHP support has been added to the developed platform. For now, OS Minix3 OS is officially supported on x86-compatible processors only. Different versions of this OS could be found but they're rather experimental. For that reason, without false modesty, we claim, that this is the first PHP script on Minix written without using x86 platform.
The Minix3 core and basic services have been ported to the 10-core processor
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- Published: Saturday, 22 September 2012 16:54
We have ported OS Minix3 and its basic services to our processor system. With transition to Minix, we’ve got both multitasking and an opportunity to work with the file system and network interfaces. Moreover, now we have a complete standard C library (earlier we had an abridged version).
10-core Xilinx Virtex5 processor with tagged shared-memory controller on FPGA has been built
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- Published: Monday, 17 September 2012 23:05
Finally! We’ve built and tested our first 10-core processor on FPGA.
General-purpose RISC core has been chosen
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- Published: Monday, 07 May 2012 03:20
For prototyping multicore processors on FPGA we’ve been looking for a core, satisfying such requirements as open flexible architecture, GCC compatibility, minimum size on FPGA, 32-bit RISC architecture, perfect 'layout' on Xilinx FPGAs, performance at least 1 DMIPS/MHz.
The team of specialists for 1000-core processor development has been formed
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- Published: Tuesday, 20 September 2011 16:20
Hello world!
