‘ExpoElectronica 2018’ exhibition has been ended


 

The 21th International exhibition of electronic components, modules and parts ‘Expoelectronica’ was held at Crocus Expo (Moscow) from 17 to 19 April 2018 simultaneously with the 16th International exhibition of Technology, equipment and materials for manufacturing devices of electronics and electrotechnical industries ‘ElectronTechExpo’.

 

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Software development kit 1.3 has been released


 

OpenCL support has been added to MALT software development kit v1.3, right now it's in test mode. Coprocessor software, required by MALT-C processor family, is a separate software module now and may be installed over MALT basic software development kit, that supports general-purpose processor cores. In the current version of the kit demo examples are separated from test scripts and located in ‘../src/sw/examples’ folder. ‘Malt_start_thr’ function, enabling to start threads with parameter transfer on slave-cores, has been implemented in Libmalt library. The support for emulated processor type selection has been added to the make scripts. When ‘MALT_SIMD=...’ variable is set, MALTemu emulator loads the corresponding dynamic library.

 

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MALTsystem at “ExpoElectronica 2018”

MALTsystem project is to be presented at “ExpoElectronica 2018” within the stand organized by our partner LLC “CEP Lomonosov Moscow State University”. We invite you to visit D207 stand. “ExpoElecrtronica” is one of the most popular exhibitions in Russia in the field of electronic components, modules and parts.

 

 

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Software development kit 1.2 has been released


 

The build program support for MALT-C 9Mb96G test chip has been added to current debugging set. Declare ‘TASIC=1’ environment variable during installation to enable compatibility mode. ‘Rm_mod’ and ‘locked’ parameters have been added to Maltemu 1.2 in ‘WriteFill’, ‘ReadModify’ functions. The support for operations with variable-length interconnect buffer has been added. Procedures of calculating the maximum allowed parallelism during required package installation have been implemented in Linux OS and FreeBSD. ‘–Hw-trace’ option, enabling to monitor function calls, has been added to MALTCC frontend.

 

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Software development kit 1.1 has been released


 

The installer is modular now! Programmer tools 'malt-tool' and 'malt_sw' system are downloaded individually. Installation directory may be changed by ‘MALT_HOME’ environment variable. By default, ‘malt-tools’ is installed to ‘/opt/MALT’ directory, ‘malt_sw’ - to ‘$HOME/MALT’. GNU development tools have been upgraded to latest versions, including gcc - up to 7.2.0 version. Manycore processor support has been added to MALTemu emulator. Thus, the performance of the emulator is almost in proportion to the number of processor cores per host system. The support for any number of arbitrary size {scalar|array} arguments has been added to MALTCC for both SIMD and slave functions.

 

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Qualcomm Centriq - 48-core server-side ARM

Qualcomm company has released 48-core server processor. The processor is developed by using 10 nm Samsung technology which enables to place on 400 mm2 area not only 48 cores but sufficiently large amount of cache memory. Qualcomm processor doesn’t lose to the latest generation of Intel Xeon processors by its characteristics and even surpasses them by some parameters...

 

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Graphcore processors for machine learning



Graphcore company has announced the creation of a new type of processors for machine learning and graph operations. They named the design IPU - Intelligence Processing Unit. According to the information from the company’s site, the device is designed for massive parallel computing using numbers with low-precision (perhaps, half-precision) floating point. It is promised, that the processor will have a much higher density of computing elements than already existing solutions in this field.

 

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The first samples of MALT-C 9Mb96G have been received from TSMC foundry


 

Samples of MALT-C 9Mb96G processor have been received from TSMC foundry (Taiwan). MALT-C 9Mb96G is the first chip belonging to MALT-C family which has been manufactured in silicon using 28 nanometer TSMC HPCPlus (high-performance computing) technological process. The processor contains 9 general-purpose RISC cores and 96 specialized processor elements integrated in 3 SIMD clusters, 32 elements each. MALT-C 9Mb96G samples have been successfully passed entry tests on test vectors on “FORMULA” chip tester and estimated characteristics have matched with achieved characteristics under full load. Thus, full power consumption at operating frequency of 800 MHz was 1 W.

 

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NEC is releasing a new vector accelerator



NEC company is going to release a vector accelerator after a long break. The device named NEC SX-Aurora TSUBASA will be manufactured using 16 nm FinFET technological process. This will be the first processor in the world equipped by six HBM2 memory modules which have been manufactured using CoWoS (Chip-on-Wafer-on-Substrate) technology.

 

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Leonhard processor for graph operations



A joint seminar with Bauman Moscow State Technical University has been held. Aleksey Popov has informed about specialized processor for graph operations developed under his leadership. The processor uses original command system named DISC (Discrete mathematics Instruction Set Computer) by the designer, enables to perform graph operations (search, insert, deletion, etc.) extremely effectively.

 

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Cisco new chip



Cisco company has presented a new specialized processor with two chips: one of them has 672 processors, 4 threads each + 44 MB SRAM + 520 SERDES with 6.5 Tb/s combined bandwidth, another one has multi-channel DRAM memory with its own controller: 1 billion random accesses per second and 37.5 GB/s during sequential read.

 

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International Blockchain Forum



On October 12 the International Blockchain Forum has taken place in Moscow. Significant part of the presentations has been devoted to ICO and other financial and legal aspects of cryptocurrency. Still, there have been some interesting topics for computer engineering specialists to discuss.

 

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Prasad Saggurti’s visit to MSU



On September 2017, there has been held a meeting of the MALT team with Prasad Saggurti - the director of development department (memory, logic libraries and memory test design) of Synopsys company.

 

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The first-generation 96-core processor project has been sent to MPW manufacturer


 

The first-generation 96-core processor project has been sent to get manufactured using MPW. VLSIs are going to be manufactured at TSMC semiconductor foundry (Taiwan) using 28 nanometer TSMC HPCPlus (high-performance computing) technological process. MALT-C 9Mb96G is the first MALT-C chip which will be manufactured “in silicon”. The processor contains 9 general-purpose RISC cores and 96 specialized processor elements integrated into 3 SIMD clusters, 32 elements each.

 

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The design of the second-generation processor has been started


 

The design of the second-generation processor has been started. The first version of processor element, which architecture is based on improved Leopard architecture, has been developed. The testing and measurement of energy consumption on target algorithms, considering time delays, have been completed in CAD Cadence at the frequency of 1 GHz for TSMC HPC+ 28 nm manufacturing process.

 

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Google Reveals Technical Specs and Business Rationale for TPU Processor



Although Google’s Tensor Processing Unit (TPU) has been powering the company’s vast empire of deep learning products since 2015, very little was known about the custom-built processor. This week the web giant published a description of the chip and explained why it’s an order of magnitude faster and more energy-efficient than the CPUs and GPUs it replaces.

 

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Applied Micro Claims Third-Generation ARM Chip Ready to Take on Intel Xeon


Applied Micro announced it is sampling X-Gene 3, its third-generation ARM SoC for servers. According to a report by The Linley Group, the new platform will provide comparable performance to the latest Intel Xeon processors, but at a significantly lower price point.



X-Gene 3 respectable performance profile is a result of its relatively high clock speed and memory bandwidth. The CPU runs its 32 cores at a base frequency of 3.0 GHz, and can achieve 3.3 GHz under turbo mode. To feed those cores with data, the chip includes eight memory channels, which can serve DDR4 devices at up to 2667 MHz, yielding 170 GB/sec of aggregate bandwidth. The SoC also includes 42 lanes of PCIe 3.0 links for external connectivity.


The report states that the X-Gene 3 can handle a “a broad range of cloud workloads, including scale-up and scale-out applications.” It should be particular adept at so-called big data applications like in-memory database processing, thanks to its superior memory bandwidth. Coincidently (or perhaps not), AMD is touting its upcoming “Naples” x86 chip for very similar memory bandwidth capabilities, based on the same 8-channel per socket design.



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The design of the first-generation 96-core MALT processor’s front end has been completed


 

The design of the first-generation 96-core processor’s front end has been completed for VLSI manufacturing at TSMC 28nm HPC+ factory (Taiwan). The basis is intended for high-performance integrated circuit development (high-performance computing, HPC). The designed processor belongs to MALT-C family. It contains 9 general-purpose RISC cores and 96 SIMD processor elements. Estimated chip area 12 mm2, power consumption 1,2 W at the frequency 0,8 GHz. Estimated date of sample delivery: January, 2018.

 

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Japan kicks off AI supercomputer project

 

 

Sunway TaihuLight supercomputer

Image: SUNWAY TAIHULIGHT SYSTEM REPORT

 

Japan has started a project to build the world's fastest supercomputer by the end of 2017.

 

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