ISC High Performance 2016 Conference

 

ISC Hight Performance 2016

Image: isc-hpc.com

SC High Performance (ISC 2016) Conference, 19-23 June, attracted 3,092 attendees from 53 countries, as well as 146 companies and research organizations showcasing their technologies and services at the ISC exhibition. 

 

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C-compiler for programmed accelerator for the MALT-Cv1 has been developed


 

We’ve developed a C-compiler which generates optimized code for programmed accelerator architecture. On target tasks the performance of the code generated by the compiler is 80% of the code performance written by a programmer in assembly language! The compiler has been developed with the use of domain-specific language (DSL) set for quick translator creation. Such DSL set enables to describe the main phases of translation. In particular, there are Prolog-like descriptions of program conversion rules and combinatorial approach to build a traversal strategy for intermediate representation graphs.

 

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We've started to create the MALT-Cv1 netlist using 28 nanometer TSMC technology


 

We've started to create the MALT-Cv1 netlist using 28 nanometer HPC+ (high-performance computing) TSMC technology. Planned area of a chip - 12 mm2. Such area is ecological optimum for pilot batch manufacturing under MPW (Multi-Project Wafer). Estimated energy consumption on a target task is 1 W, which enables to achieve considerably higher energy efficiency calculations than on a CPU and GPU.

 

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Assembler and emulator for programmed accelerator have been developed as parts of MALT


 

We’ve developed an assembler, maintaining algebraic syntax similar to the one used in C language. Along with that, a program, implemented on the assembler, is also proper for C language. That beneficial side effect of the use of algebraic notation enabled to implement system software modeling for programmed accelerator with high performance via a normal C compiler.

 

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Leopard processor element for vector MALT coprocessor has been designed


 

The development of a processor element for vector accelerator Leopard has been accomplished. The processor element architecture has been chosen according to the requirements for maximum flexibility (from a programming perspective) at high performance and energy efficiency on target tasks. As a result, the architecture based on ALU tree has been chosen.

 

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The development of MALT-processors with vector and mixed architecture has been started


 

The development of MALT-processors with vector and mixed architecture has been started.

 

Solutions of mathematical tasks with the ultimate level of complexity from the field of discrete mathematics with perfect or almost perfect parallelization of data with regards to compact (according to core size) and particularly complex mathematical procedures may be energy-efficient implemented only on specialized programmed or configurable computing structures on FPGA/VLSI or in the form of CPU/GPU blocks.

 

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210-core processor on FPGA Xilinx Virtex7 has been built


 

Recently we’ve finished the assembling and debugging of a new monster - 210-core processor prototype on FPGA Xilinx Virtex7 2000T. This is the biggest chip in the 7th generation of Xilinx FPGA. And our MALT system is the largest array of independent 32-bit RISC cores prototyped on a single FPGA known today.

 

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A new smart memory controller with DMA support has been developed


 

A new version of the smart memory controller has been developed and tested. Now the controller maintains block data transfers - usually this calls ‘DMA’ - a system, enabling to copy data from one memory area to another without involving processing cores. The usage of the mechanism allows to increase performance of intensive data exchange tasks in several times. There is a basic set of "real" atomic operations in the controller, for instance, atomic increment is supported.

 

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ISC'14

 

ISC’14 was held June 22-26 in Leipzig, Germany. ISC is the world’s oldest and the most significant high-performance computing conference and exhibition in Europe for the global HPC community.

 

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The developed architecture is named ‘MALT’


 

We’ve been thinking long and hard over what name to give our architecture. Eventually, after long deliberation, we’ve decided to name it ‘MALT’ - Manycore Architecture with Lightweight Threads.

 

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49-core processor on Xilinx Virtex6 FPGA with lightweight-thread support has been built


 

This is a significant milestone in the history of the project development. A multi-threaded processor, containing 49 RISC cores, has been implemented on Xilinx Virtex6 FPGA. The architecture, completely redesigned since 10-core prototype, provides the ability to effectively load dozens and hundreds of simple computing cores without conflicts and excessive overhead expenses.

 

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Supercomputer summer classes

 

Supercomputer summer classes are held at the Faculty of Computational Mathematics and Cybernetics of the Academy, SRCC, REC "Supercomputer technology" from June 24 to July 6, 2013.

 

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ISC 2013

 

ISC’13 was held June 16-20 in Leipzig, Germany. ISC is the world’s oldest and the most significant high-performance computing conference and exhibition in Europe for the global HPC community.

 

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Original on-chip bus for combining hundreds of processing cores has been developed


 

The development of simple packet bus (SPBUS), enabling to ensure connectivity of hundreds of different devices inside a chip, is finished. SPBUS implementation is written entirely on VHDL without using closed source licensed IP. The developed bus is exceptionally compact in terms of FPGA or VLSI hardware resources usage, along with that it provides delays less than 50 cycles during data transfer.

 

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The first PHP script on Minix written without using x86 platform!


 

PHP support has been added to the developed platform. For now, OS Minix3 OS is officially supported on x86-compatible processors only. Different versions of this OS could be found but they're rather experimental. For that reason, without false modesty, we claim, that this is the first PHP script on Minix written without using x86 platform.

 

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