 |
We are growing and strive to provide our employees with a comfortable working environment. Moreover, the pandemic requires large and clean working spaces. In the spring of 2020, we needed to move. We gathered our team and tried to formulate what we want. Here's what we finally wrote...
 |
MaltSystem specialists have developed a new development board that will allow teams to quickly start working with the MALT-Cv2
 |
Samples of MALT-Сv2 processor have been received from TSMC. MALT-Сv2 samples have been successfully passed functional tests. Achieved processor characteristics match estimated characteristics. The processor has a programmable fully digital PLL – FDPLL.
 |
Our project has entered into an agreement to gain access to 16 nm technologies at the TSMC.
 |
 |
The 5th Anniversary International Forum "Microelectronics-2019" was held from September 30 to October 5.
 |
A new version of MALT_SDK is available. MALT_SDK v1.8 allows to expand the capabilities of users.
August 2019. We completed work on a prototype SoC MALT-Cv2 by sending the project to the TSMC. The MALT will be manufactured using the 28 nm TSMC HPCPlus process technology (high-performance computing). The processor contains 20 general-purpose RISC cores and 480 specialized processor elements combined in 15 SIMD clusters of 32 elements each. The calculated value of the total power consumption was 6.0 W.
Released development kit version 1.7.
June 26, 2019. Faculty of Physics, Lomonosov Moscow State University, and Synopsys held a workshop at the MSU on the technical aspects of developing specialized processors with a problem-oriented instruction set.
On June 26, 2019, Synopsys in collaboration with Moscow State University organizes a free seminar covering various aspects of the design process of specialized processors: from introducing the design concept and software and hardware optimization space to the latest case studies of this technology.
The first samples of MALT-484PS-01 debugging module have been released. The module is designed on Xilinx Kintex7 FPGA with implemented MALT-Cv2 prototype and intended to learn the processor’s hardware and software, to debug system and applied software and to prototype target devices.
On April 17 Sergey Elizarov, the MALT project leader, has delivered the presentation within the investment session organized by the Consortium of Microelectronics Design Centers at ExpoElektronica-2019 exhibition.
Software development kit 1.6 for MALT environment contains modifications and improvements to simplify developer’s work with the system.
On January 23, the physical faculty of Lomonosov Moscow State University along with Mentor, a Siemens Business company has held a seminar on the topic of “VLSI design by Mentor CAD facilities”. Sergey Elizarov, the MALT project leader, has made a welcoming speech.
The development of the second-generation MALT-C (working name: MALT-Cv2) behavior model has been completed, the processor has been successfully synthesized, using 28 nm TSMC technology.
The MALT project has participated in international exhibition “Electronica-2018” that took place in Munich (Germany) from 13 to 16 November 2018. “Electronica-2018” has gathered manufacturers, designers, distributors and customers from various countries at one place and has been recognized as the world’s largest event in the field of electronic components, systems and electronics industry applications.
From 13 to 16 November 2018 MALT project will participate in international exhibition of electronic components, systems and electronics applications “Electronica-2018” that will take place in Munich (Germany).
At the beginning of October 2018, an international forum “Microelectronica 2018” has taken place in Alushta (Crimea). We’ve taken an active part at the meeting, Sergey Elizarov, the MALT project leader, has made a presentation on the topic “Multicore computing system testing based on RSA algorithm ideas”.
SDK v1.5 released
2012—2021 © All rights reserved.