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The work related to the design of the MALT-Cv3 processor (Enceladus) was completed in the second quarter of this year. The project was sent to the TSMC factory for the production run of the chip using the TSMC 16 nm technology.
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We are pleased to announce that the MALT-Cv3 "Enceladus" processor has been successfully synthesized in the TSMC 16 nm technology base.
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The first samples of the new debugging board for the MALT-Cv2 are available! The board allows to test the execution of software tasks on the MALT-Cv2 processor, as well as to check the functioning of the FDPLL prototype in the entire spectrum of acceptable input frequencies according to LVDS and CMOS standards.
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We are growing and strive to provide our employees with a comfortable working environment. Moreover, the pandemic requires large and clean working spaces. In the spring of 2020, we needed to move. We gathered our team and tried to formulate what we want. Here's what we finally wrote...
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Our company continues to develop FDPLL. At this stage of the work, the FDPLL has been successfully synthesized in 16 nm TSMC.
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MaltSystem specialists have developed a new development board that will allow teams to quickly start working with the MALT-Cv2
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The project of creating a new extremely compact embedded processor for processing network traffic MALT-Cv3 (commercial name is "Enceladus") has moved into the final debugging phase of RTL and we are finally ready to tell you something about this product.
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The development of FDPLL is one of the current projects of our company. At this stage of the work, we have successfully completed the synthesis of FDPLL in 28 nm TSMC.
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Samples of MALT-Сv2 processor have been received from TSMC. MALT-Сv2 samples have been successfully passed functional tests. Achieved processor characteristics match estimated characteristics. The processor has a programmable fully digital PLL – FDPLL.
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Our project has entered into an agreement to gain access to 16 nm technologies at the TSMC.
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The 5th Anniversary International Forum "Microelectronics-2019" was held from September 30 to October 5.
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A new version of MALT_SDK is available. MALT_SDK v1.8 allows to expand the capabilities of users.
August 2019. We completed work on a prototype SoC MALT-Cv2 by sending the project to the TSMC. The MALT will be manufactured using the 28 nm TSMC HPCPlus process technology (high-performance computing). The processor contains 20 general-purpose RISC cores and 480 specialized processor elements combined in 15 SIMD clusters of 32 elements each. The calculated value of the total power consumption was 6.0 W.
Released development kit version 1.7.
June 26, 2019. Faculty of Physics, Lomonosov Moscow State University, and Synopsys held a workshop at the MSU on the technical aspects of developing specialized processors with a problem-oriented instruction set.
On June 26, 2019, Synopsys in collaboration with Moscow State University organizes a free seminar covering various aspects of the design process of specialized processors: from introducing the design concept and software and hardware optimization space to the latest case studies of this technology.
The first samples of MALT-484PS-01 debugging module have been released. The module is designed on Xilinx Kintex7 FPGA with implemented MALT-Cv2 prototype and intended to learn the processor’s hardware and software, to debug system and applied software and to prototype target devices.
On April 17 Sergey Elizarov, the MALT project leader, has delivered the presentation within the investment session organized by the Consortium of Microelectronics Design Centers at ExpoElektronica-2019 exhibition.
Software development kit 1.6 for MALT environment contains modifications and improvements to simplify developer’s work with the system.
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